I am new to develop or generate clocking requirements. I am working on a project of verification where I need to generate(manipulate) clocks which supports Spread spectrum clocking and include different types of jitter to manipulate clock. I searched a lot online but could not find any particular source to look through. Can anyone help me regarding this?
In reply to dave_59:
yes , I tried but unfortunately could not find anything relevant. I need to understand from basic application of SSC(How and When SSC applied) , how SSC effects data transmission on high rate clock frequency plus calculation of clock frequency while SSC is applied.
In reply to meeteedesai:
In reply to dave_59:
yes , I tried but unfortunately could not find anything relevant. I need to understand from basic application of SSC(How and When SSC applied) , how SSC effects data transmission on high rate clock frequency plus calculation of clock frequency while SSC is applied.
SSC is not really relevant on RT level. This is a physical topic.
For details look here:
In reply to chr_sue:
I read the link provided by you and that make sense that SSC is used for reducing EMI.
So why do we need to manipulate clock while running simulation of Serdes data transmission? what is the purpose of SSC enabled clock in simulation ? If I am not wrong, is it just that SSC introduce additional jitter and we have to take care of jitter while transmitting SERDES data over channel we manipulate clock to verify data transmission.correct?
In reply to meeteedesai:
The RTL simulation does not really take care for the jitter. It looks only on edges. The jitter is a sopecific topic which can be considered on gate level, because there you are considering the timing of the clock.
A typical approach is to develop your digital RTL and verify this without jitter. On gatelevel you can introduce the jitter an try to validate your design is still working.
In reply to chr_sue:
okay so for gate-level simulation we need to generate this kind of manipulation of clocks, but there is no such information online that how to manipulate SSC clocks or generate SSC (jitter inclusive) clocks for gate level simulation also. My requirement for the project is to configure a clock when needed SSC clocking and generate clk according to the configuration for verification. Even on the PCIE documentation it says that they provide the features in VIP but in my case we do not have any VIP so I need to generate the clock according to specification.
In reply to meeteedesai:
Your spec should give you information about the jitter, i.e. walking clock edges and changes in the clock width.