In reply to chr_sue:
okay so for gate-level simulation we need to generate this kind of manipulation of clocks, but there is no such information online that how to manipulate SSC clocks or generate SSC (jitter inclusive) clocks for gate level simulation also. My requirement for the project is to configure a clock when needed SSC clocking and generate clk according to the configuration for verification. Even on the PCIE documentation it says that they provide the features in VIP but in my case we do not have any VIP so I need to generate the clock according to specification.