Signal stable in precondition on SVA

SystemVerilog
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1

Hi,

I have a property to check if the data is stable while some signal is zero, something like:

~arb |=> $stable(data)

This is true only if a clear signal is not activated.
I am using a flop to store a flag if the clear signal is asserted during the transaction, and checking it in the precondition:

~arb & ~is_cleared |=> $stable(data)

I don’t like this solution, is not elegant and it needs many logic to manage the flop load and clear.
Any idea of how to do it only with SVA in a better way?

Thank you

2

In reply to meleth:
Support logic is often used in assertions. I don’t see anything wrong with it.
You may want to consider the sync_accept_on or the asynchronous accept_on where when the expression is true, the assertion is vacuous. FOr example:


ap_accept_disable : assert property (@ (posedge clk)
  disable iff (!reset_n)
  sync_accept_on (A_signal) // maybe something used in the generation of "is_cleared"
  !arb |=> $stable(data));

I hate the use of the unary “~” for logical negation because the “~” has a different connotation.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
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  3. Papers:

Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
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3

In reply to ben@SystemVerilog.us:

In reply to meleth:
Support logic is often used in assertions. I don’t see anything wrong with it.
You may want to consider the sync_accept_on or the asynchronous accept_on where when the expression is true, the assertion is vacuous. FOr example:


ap_accept_disable : assert property (@ (posedge clk)
disable iff (!reset_n)
sync_accept_on (A_signal) // maybe something used in the generation of "is_cleared"
!arb |=> $stable(data));

I hate the use of the unary “~” for logical negation because the “~” has a different connotation.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books: Component Design by Example https://rb.gy/9tcbhl
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers:

Yes, of course there it nothing wrong to use logic, but I always try to reduce it as much as possible. The sync_accept_on was exactly what I was looking for,

Thank you a lot