In reply to meleth:
Support logic is often used in assertions. I don’t see anything wrong with it.
You may want to consider the sync_accept_on or the asynchronous accept_on where when the expression is true, the assertion is vacuous. FOr example:
ap_accept_disable : assert property (@ (posedge clk)
disable iff (!reset_n)
sync_accept_on (A_signal) // maybe something used in the generation of "is_cleared"
!arb |=> $stable(data));
I hate the use of the unary “~” for logical negation because the “~” has a different connotation.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…
- SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
- Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb - Papers:
- Understanding the SVA Engine,
Verification Horizons - July 2020 | Verification Academy - SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/