Hi,
I want to know a sequence so that I can validate my assertion.
i just need a signal who will get only one pulse
at t=0 pulse 0
next clock t=1 pulse 1
next clock t=2 pulse 0
next clock t=3 pulse 0 and then pulse should be 0 throughout.
sequence pulse_check;
@(posedge clk)
((pulse==1) ##1 (pulse==0)[*20:$] );
endsequence
but this make pulse low for 20 cycles. I want this pulse to be low till the end of simulation
In reply to probilkumar:
module m;
let n=2**30;
bit a, clk;
sequence q;
!a ##1 a[*n];
endsequence
initial ap_init: assert property(@(posedge clk) q);
endmodule
// See 1800'2017 11.4.3 Arithmetic operators
// Table 11-6—Examples of modulus and power operators
// a ** b is a to the power of b
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…
In reply to probilkumar:
$rose(pulse) |=> always !pulse;
Mentor, Questa, Aldec - all support this.
VCS version available on EDA playground does Not, latest versions could support.
In reply to ssureshgverifier@gmail.com:
From 1800’2017 16.12.11 Always property
//Implicit form:
implicit_always: assert property(p);
//Explicit form:
initial explicit_always: assert property(always p);
/*This is not shown as a practical example, but only for illustration of the meaning of always. Examples:*/
initial a1: assume property( @(posedge clk) reset[*5] #=# always !reset);
/*The assertion a1 says that reset shall be true for the first 5 clock ticks and then remain 0 for the rest of the computation. */
Thus, in the above solution you would need the initial, Otherwise, you have a new attempt at every clock edge. You might argue that since there is no rose of pulse, the new attempts are vacuous, you are correct. However, why putting more stress on the simulator. In addition, it does not read correctly since the always takes care of future clocks; it is the the explicit form of the always.
initial ap_pulse: assert property(@(posedge clk)
$rose(pulse) |=> always !pulse);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…