Sequence to check signal is high for 1 clock cycle and the low throughout the simulation

SystemVerilog
, ,
2

In reply to probilkumar:


module m;
  let n=2**30; 
  bit a, clk; 
  sequence q;
     !a ##1 a[*n]; 
  endsequence 
  initial ap_init: assert property(@(posedge clk) q);  
endmodule
// See 1800'2017 11.4.3 Arithmetic operators 
//               Table 11-6—Examples of modulus and power operators
//  a ** b is a to the power of b

Ben Cohen
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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