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What is the difference between
a. ~X (where X is a signal name)
b. !X
c. $fell(X)
Please explain with examples -
How can i write assertion for “signal a must not rise if signal b is low”?
The ~ and ! operators are clearly described in the SystemVerilog LRM with examples. See section 11.4 Operator Descriptions. Do you have a copy?
There are no examples of $fell on its own in the LRM; it is usually used in the context of an assertion where there is a reference clock cycle. $fell(X) returns true if the LSB of X is 0 in the current cycle when it was not 0 in the previous cycle.
There is no $rise() in SystemVerilog, only the past tense $rose(). Since this is digital logic simulation, not analog, you can only know that a signal rises after it has already risen.
So you can write
assert property(@posedge clk !b |-> !$rose(a));
But it is easier to understand this property by simplifying it using DeMorgan’s Law.
assert property(@posedge clk !$rose(a) |-> b);
In reply to dave_59:
Thanks for the solution…but i didnt find the topic in systemverilog3.1a LRM in chapter 11
In reply to Sourav:
You are using an extremely old version of the LRM which only describes the extensions to Verilog. Get the latest LRM
In reply to dave_59:
Thanks for the solution…but i didnt find the topic in systemverilog3.1a LRM in chapter 11
Looking at very old, non standard LRM, also that was just SV part, and not Verilog included (Your first question was more of Verilog). IEEE SV 1800-2009/2012 merged Verilog into erstwhile, old SV LRM and is now freely available for download. See: http://cvcblr.com/?p=844
Good Luck
Srini
In reply to Srini @ CVCblr.com:
@Dave I think you made a mistake with your DeMorgan simplication:
!b |-> !$rose(a) === b or !$rose(a)
Additionally, it might also be easier to write it in the form:
!$rose(a) |-> b // applying DeMorgan leads to !$rose(a) or b which is the same as above
In natural language, instead of saying “a mustn’t rise when b is low”, you say “if a rose, then b was high”.