In reply to dave_59:
Thanks for the solution…but i didnt find the topic in systemverilog3.1a LRM in chapter 11
Looking at very old, non standard LRM, also that was just SV part, and not Verilog included (Your first question was more of Verilog). IEEE SV 1800-2009/2012 merged Verilog into erstwhile, old SV LRM and is now freely available for download. See: http://cvcblr.com/?p=844
Good Luck
Srini