Questions to exercise my SystemVerilog, Assertions and UVM skills

I’m looking for few sources where i can exercise my UVM, SystemVerilog and Assertions skills by answering few of the programming questions which can be completed within an hour.
Could you please suggest few links/materials/sources (preferably with solution but even otherwise its Okay )??

In reply to vvv:

A commercial option with analysis is available at:
There is also free version of these Quizzes on case to case basis. Contact via that link to learn more.


In reply to Srini @

page not found