Need inputs or suggestions for cover property coding style and debugging using generate block

SystemVerilog
1

HI ALL,

REFERENCE : Assertion using Generate Block | Verification Academy

The below following code is my assertion,
From the above link,got the solution and able to generate cover property for 320 different TX_DATA values.

Question 1) In the following assertion I want to change tx to rx datalane so that I can check for the rx data lane.
Can I pass the signal name in the sequence so that it will be generic for both tx and rt data lane?

Question 2)(strap_freerunstrben_h == freerunstrben_h)- I am passing value to the signal.I want both LHS and RHS to be passing from the sequence.i.e signal and value both. ( EXAMPLE : sequence ev_frs0_rat2_x8_wid8_tx_pa(strap_freerunstrben_h(singal name),freerunstrben_h(signal value);

Question 3) I am generating 320 cover properties using generate block.when the cover property hits the display statement(below code) prints the current value of the property.Other than this is there any way to print the current values passing to the cover property.(Like adding a display statement inside the generate block some thing like that (we cannot use its compilation error))

Question 4) This is the cover property used "cp_frs0_rat2_x8_wid8_tx_pa: cover property (ev_frs0_rat2_x8_wid8_tx_pa(1’b0,2**(i-1)));"i want to make “cp_frs0_rat2_x8_wid8_tx_pa” generic so that i can make some thing like this cp_frs[j]_rat[j+2]_x8_wid8_tx_pa_i…[0-319].
Can i do this?

sequence ev_frs0_rat2_x8_wid8_tx_pa(logic freerunstrben_h ,bit [319:0] TX_DATA);
@(posedge ickopi_txclk0)
((strobelane0_txactive==1’b1) && (strap_freerunstrben_h == freerunstrben_h) && (strobelane0_powerstate[1:0]== 2’b10) && (strobelane0_rate[1:0]== 2’b10) && (validlane0_txdata[7:0]== 8’h00)) ##1 ((strobelane0_txactive== 1’b1) && (strap_freerunstrben_h == freerunstrben_h) && (strobelane0_powerstate[1:0]== 2’b10) && (strobelane0_rate[1:0]== 2’b10) && (validlane0_txdata[7:0]== 8’hFF)) ##1 ((strobelane0_txactive == 1’b1) && (strap_freerunstrben_h == freerunstrben_h) && (strobelane0_powerstate[1:0]== 2’b10) && (strobelane0_rate[1:0]== 2’b10) && (validlane0_txdata[7:0]== 8’h00) && ({datalane39_txdata[7:0],datalane38_txdata[7:0], datalane37_txdata[7:0],datalane36_txdata[7:0],datalane35_txdata[7:0],datalane34_txdata[7:0],datalane33_txdata[7:0], datalane32_txdata[7:0],datalane31_txdata[7:0],datalane30_txdata[7:0],datalane29_txdata[7:0],datalane28_txdata[7:0], datalane27_txdata[7:0],datalane26_txdata[7:0],datalane25_txdata[7:0],datalane24_txdata[7:0], datalane23_txdata[7:0],datalane22_txdata[7:0],datalane21_txdata[7:0],datalane20_txdata[7:0], datalane19_txdata[7:0],datalane18_txdata[7:0],datalane17_txdata[7:0],datalane16_txdata[7:0], datalane15_txdata[7:0],datalane14_txdata[7:0],datalane13_txdata[7:0],datalane12_txdata[7:0], datalane11_txdata[7:0],datalane10_txdata[7:0],datalane9_txdata[7:0],datalane8_txdata[7:0], datalane7_txdata[7:0],datalane6_txdata[7:0],datalane5_txdata[7:0],datalane4_txdata[7:0],datalane3_txdata[7:0], datalane2_txdata[7:0],datalane1_txdata[7:0],datalane0_txdata[7:0]}== TX_DATA),$display(“TX_DATA = %h \n”, TX_DATA));
endsequence
//cp_frs0_rat2_x8_wid8_tx_pa0: cover property (ev_frs0_rat2_x8_wid8_tx_pa(TX_DATA));

    bit [319:0] TX_DATA = 320'b1;
generate
          for(genvar i=0;i<320;i++)
              begin 
		if(i == 0)
		    begin	
           	    cp_frs0_rat2_x8_wid8_tx_pa_0: cover property (ev_frs0_rat2_x8_wid8_tx_pa(1'b0,320'b0)); 
		    end 
	begin : assert_array
           cp_frs0_rat2_x8_wid8_tx_pa: cover property (ev_frs0_rat2_x8_wid8_tx_pa(1'b0,2**(i-1))); 
	end 
	end 
endgenerate

I think mail is bit long.
Suggestions would be really helpful.I am trying to make almost 4000+ cover properties into one generic cover property(TX,RX,and for 40 lane.Need to include for each and every lane). when generated I want to make it easy in terms of debug perspective also.

Thanks In Advance.

-Regards,
-Raja

2

The below following code is my assertion,
From the above link,got the solution and able to generate cover property for 320 different TX_DATA values.
Question 1) In the following assertion I want to change tx to rx datalane so that I can check for the rx data lane.
Can I pass the signal name in the sequence so that it will be generic for both tx and rt data lane?

[Ben] Yes, this is standard Verilog stuff where the actual arguments are passed to the formal arguments.

Question 2)(strap_C == C)- I am passing value to the signal.I want both LHS and RHS
to be passing from the sequence.i.e signal and value both.
( EXAMPLE : sequence q_A(strap_C(singal name),C(signal value);

[Ben] From LRM
sequence_declaration ::=
sequence sequence_identifier [ ( [ sequence_port_list ] ) ] ;
{ assertion_variable_declaration }
sequence_expr ; // a number is a sequence expression
endsequence [ : sequence_identifier ]
Thus, I could declare something like:


module k; 
	int data, check; 
	bit sync, clk_fast; 
	sequence q(int a, b, bit c, clk); 
      @(posedge clk) c ##1 a==b; 
    endsequence
  // and using it like: 1'b
  cover sequence(q(data, 32'hFF00_0000, sync, clk_fast)); 
endmodule

Question 3) I am generating 320 cover properties using generate block.when the cover property hits the display
statement(below code) prints the current value of the property.Other than this is there any way to print
the current values passing to the cover property.(Like adding a display statement inside the
generate block some thing like that (we cannot use its compilation error))

[Ben] LRM states:
sequence_match_item ::=
operator_assignment
| inc_or_dec_expression
| subroutine_call
Thus, you can only use the $display system function, or a user defined function.
If you use a user-defined function, you could pass an actual argument to not display the values once you’re happy with the operations.
Question for you: WHY are you using “cover property” for a sequence? From LRM
[1] The results of coverage statement for a property contain:
 Number of times attempted
 Number of times succeeded
 Number of times succeeded because of vacuity

Results of coverage for a sequence include:
 Number of times attempted
 Number of times matched (each attempt can generate multiple matches).
In addition, statement_or_null gets executed for every match.
If there are multiple matches at the same time, the statement gets
executed multiple times, one for each match.

Question 4) This is the cover property used "cp_frs0_rat2_x8_wid8_tx_pa: cover property
(q_A(1’b0,2**(i-1)));"i want to make “cp_frs0_rat2_x8_wid8_tx_pa” generic
so that i can make some thing like this cp_frs[j]_rat[j+2]_x8_wid8_tx_pa_i…[0-319].
Can i do this?

[Ben] Yes.

A general comments: If you have access to a simulator, many of these questions can be answered trying out simple code.
Of course, the LRM is also a good source of information … and so is my SVA book (… a plug) :)

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks for the info.

Question for you: WHY are you using “cover property” for a sequence? From LRM
Yes I dont know why they used in the previous project, i have ported and changed the code.
I need some example for Question 3.That would be really helpful.
Yes I have tried all the questions with the sample code too.

I am referring your SVA book only for coding style…:-)

-Regards,
-Raja.

4

In reply to sraja:

module sq1;
/* Question 3) I am generating 320 cover properties using generate block.when the cover property hits the display
statement(below code) prints the current value of the property.Other than this is there any way to print
the current values passing to the cover property.(Like adding a display statement inside the
generate block some thing like that (we cannot use its compilation error))*/


    bit clk, a, b, enb; 
    int data;
    function void show(bit enb, int data);
        if(enb) $display("data= %d", data);
    endfunction 
    ap_cv: cover sequence (@ (posedge clk)
            a ##[1:5] b ##0 (data==0, show(enb, data))); 
endmodule