In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks for the info.
Question for you: WHY are you using “cover property” for a sequence? From LRM
Yes I dont know why they used in the previous project, i have ported and changed the code.
I need some example for Question 3.That would be really helpful.
Yes I have tried all the questions with the sample code too.
I am referring your SVA book only for coding style…:-)
-Regards,
-Raja.