Need inputs or suggestions for cover property coding style and debugging using generate block

SystemVerilog
2

The below following code is my assertion,
From the above link,got the solution and able to generate cover property for 320 different TX_DATA values.
Question 1) In the following assertion I want to change tx to rx datalane so that I can check for the rx data lane.
Can I pass the signal name in the sequence so that it will be generic for both tx and rt data lane?

[Ben] Yes, this is standard Verilog stuff where the actual arguments are passed to the formal arguments.

Question 2)(strap_C == C)- I am passing value to the signal.I want both LHS and RHS
to be passing from the sequence.i.e signal and value both.
( EXAMPLE : sequence q_A(strap_C(singal name),C(signal value);

[Ben] From LRM
sequence_declaration ::=
sequence sequence_identifier [ ( [ sequence_port_list ] ) ] ;
{ assertion_variable_declaration }
sequence_expr ; // a number is a sequence expression
endsequence [ : sequence_identifier ]
Thus, I could declare something like:


module k; 
	int data, check; 
	bit sync, clk_fast; 
	sequence q(int a, b, bit c, clk); 
      @(posedge clk) c ##1 a==b; 
    endsequence
  // and using it like: 1'b
  cover sequence(q(data, 32'hFF00_0000, sync, clk_fast)); 
endmodule

Question 3) I am generating 320 cover properties using generate block.when the cover property hits the display
statement(below code) prints the current value of the property.Other than this is there any way to print
the current values passing to the cover property.(Like adding a display statement inside the
generate block some thing like that (we cannot use its compilation error))

[Ben] LRM states:
sequence_match_item ::=
operator_assignment
| inc_or_dec_expression
| subroutine_call
Thus, you can only use the $display system function, or a user defined function.
If you use a user-defined function, you could pass an actual argument to not display the values once you’re happy with the operations.
Question for you: WHY are you using “cover property” for a sequence? From LRM
[1] The results of coverage statement for a property contain:
 Number of times attempted
 Number of times succeeded
 Number of times succeeded because of vacuity

Results of coverage for a sequence include:
 Number of times attempted
 Number of times matched (each attempt can generate multiple matches).
In addition, statement_or_null gets executed for every match.
If there are multiple matches at the same time, the statement gets
executed multiple times, one for each match.

Question 4) This is the cover property used "cp_frs0_rat2_x8_wid8_tx_pa: cover property
(q_A(1’b0,2**(i-1)));"i want to make “cp_frs0_rat2_x8_wid8_tx_pa” generic
so that i can make some thing like this cp_frs[j]_rat[j+2]_x8_wid8_tx_pa_i…[0-319].
Can i do this?

[Ben] Yes.

A general comments: If you have access to a simulator, many of these questions can be answered trying out simple code.
Of course, the LRM is also a good source of information … and so is my SVA book (… a plug) :)

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115