Assertion using Generate Block

HI,

I am trying to Create multiple instances of cover properties using generate block.PF the code below,

generate
    for (genvar i = 0; i < 3; i++) begin 
     //TX_DATA = 64'b1 << 1;
    begin : assert_array_i
    cp_x8_wid8_tx_pa0: cover property (ev_x8_wid8_tx_pa0(TX_DATA)); 
    end
    end
endgenerate

TX_DATA is initialized to 64’b1;
for next instances it is 64’b1 << 1, – > 2
next → 4,8,16…

My intention is to create multiple instances of cover properties and pass the TX_DATA with different value and compare it.
How to shift and pass the value to assertion ,TX_DATA = 64’b1 << 1?
As generate block dose not accept procedural assignments.

-Regards,
Sravan.

In reply to sraja:

I want to know is there any way to pass the value, while creating cover property/assertion using in the generate block?

Can you try like this :



 bit [63:0]TX_DATA[3];
 genvar    i;
  
generate
for ( i = 0; i < 3; i++)
  begin
   TX_DATA[i] = 64'b1 << i;
     cp_x8_wid8_tx_pa0: cover property (ev_x8_wid8_tx_pa0(TX_DATA[i])); 
  end
endgenerate


How about

for(genvar TX_DATA=1; TX_DATA<17; TX_DATA<<=1) // or TX_DATA = TX_DATA<<1;
 begin : assert_array_i
    cp_x8_wid8_tx_pa0: cover property (ev_x8_wid8_tx_pa0(TX_DATA)); 
 end

In reply to cool_cake20:

cool_cake20, how about trying out your answer with a simple test before posting to see if it works.

In reply to dave_59:

Hi Dave,

    Thanks for the suggestion. I have tried with small example, however i did mistake in my example.

the OP has mentioned that assignments are not happening in generate block.But the fact is that variable assignment has to happen in procedural blocks so problem is not with the generate block.

Here is my example , i should have realized what was the actual problem in OP code.




module test;
bit [63:0]TX_DATA[3];
genvar    i;
  
generate
for ( i = 0; i < 3; i++)
  begin
     initial
	begin
	   TX_DATA[i] = 64'b1 << i;
	   $display("the value=%0b",TX_DATA[i]);
	end
  end
   
endgenerate
   
endmodule // test


In reply to dave_59:

Hi Dave,

Thanks for the reply.I want to send the data after shifting.But it dose not work the the way i need/intended.

I will mention my piece of code and requirement below,

sequence ev_frs0_rat2_x8_wid8_tx_pa0(bit [63:0] TX_DATA);
@(posedge ickopi_txclk)
sequence logic … iopi_datalane0_txdata[63:0]== TX_DATA));
endsequence

              for (i = 0; i < 3; i++) begin 
		initial
	begin
	   TX_DATA = 64'b1 << i;
	   $display("the value=%0b",TX_DATA);
           begin : assert_array_i
           cp_frs0_rat2_x8_wid8_tx_pa0: cover property (ev_frs0_rat2_x8_wid8_tx_pa0((TX_DATA))); 
           end
	end
***Note : This code is not working,It will have the final value TX_DATA = 4;//100 for all the instances created.which is not intended.
  1. I want to pass the TX_DATA with different value while generating the assertion in the generate block.

    i.e…, TX_DATA = 1,TX_DATA=2,TX_DATA=4,TX_DATA=8,16,… up-to TX_DATA[63] ==1.
    For this i want to shift each data and send it through the generated assertion.

    So, Adding from your code i think i need two variables one to loop and other to store the shift data and pass it to the assertion.

  2. I want to pass the value and print it and see whether i am send it correctly or not.

4)I am trying in other way if it works i will reply on it.

Thanks for the reply to cool_cakes and Dave

-Regards,
-Raja.

In reply to sraja:

HI Dave,

The Following code is working ,

generate
          for(genvar i=0;i<3;i++)
	begin : assert_array
           cp_frs0_rat2_x8_wid8_tx_pa0: cover property (ev_frs0_rat2_x8_wid8_tx_pa0(**2**i**)); 
	end 
endgenerate

    sequence ev_frs0_rat2_x8_wid8_tx_pa0(bit [63:0] TX_DATA);
    @(posedge ickopi_txclk)
    .................... iopi_datalane0_txdata[7:0]}== TX_DATA)); 
    endsequence

I can pass the value to TX_DATA parameter.Before sending I want to confirm/print the value to see i am passing particular value.
Can I do it?

-Regards,
-Raja.

In reply to sraja:

Hi sraja,

      Regarding Dave's example, it should work, you don't need two variables for iteration and shift. 

With loop variable only you can achieve that.The only thing is that increment condition should has to be less than your 2**N where N=number of bit positions you want shift.

See here example :


module test2;

   bit [63:0] TX_DATA;
   
   task automatic display_tx(input int xyz);
      #(1 * xyz);
      $display("time=%0t ,The value=%0d",$time,xyz);
   endtask // display_tx
   
   generate  
      for(genvar TX_DATA=1; TX_DATA<17; TX_DATA<<=1) // or TX_DATA = TX_DATA<<1;
	begin 
	   initial
	     begin
		display_tx(TX_DATA);
	     end
	end
   endgenerate
   

   
endmodule // test2


And the simulation results :


VSIM 1> run -all
# time=1 ,The value=1
# time=2 ,The value=2
# time=4 ,The value=4
# time=8 ,The value=8
# time=16 ,The value=16


Regarding my example :

You need to declare TX_DATA as an array (please see my previous post) and i am not sure why you have omitted the for loop from generate block.

simulation output of my example :



VSIM 1> run -all
# the value=1
# the value=10
# the value=100


Please run it and see.

In reply to cool_cake20:

Hi,

Yes Daves example is working.My Intent is to display value before passing it to the assertion.
If I display value,I can know what value i am send to the assertion.(For debugging purpose)

-Regards,
-Raja.

In reply to sraja:

Hi Dave,

The code above is working.

I want to see the value before i send it to the assertion.Is there any possibilty to see the value.(For debug purpose… i want it.)

cp_x8_wid8_tx_pa0: cover property (ev_x8_wid8_tx_pa0(TX_DATA)); —> To Print TX_DATA Value.

-Regards
-Raja.

In reply to sraja:

I think there may be some confusion as you do not “send” a value to an assertion/cover construct. They are declarations of concurrent processes. What you can do is

for(genvar i=0;i<3;i++)
  begin : assert_array
  initial $display("%m value is %0d", 2**i);
   cp_frs0_rat2_x8_wid8_tx_pa0: cover property (ev_frs0_rat2_x8_wid8_tx_pa0(2**i));
   end

You can also embed $display statements in your sequence. See section 16.11 Calling subroutines on match of a sequence in the 1800-2012 LRM