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I am getting error when re-simulating design using questasim command vsim counter -vcdstim counter.vcd
i modified bitwidth field from vector to 1 bit
Example
$var reg 8 # count [7:0] $end
modified to
$var reg 1 # count [0] $end
$var reg 1 # count [1] $end
…
$var reg 1 # count [7] $end
now its working
why i am not getting results with vector definition $var reg 8 # count [7:0] $end ?
Hi,
As VCD file format is ieee standard.All simulators has to support the format.
But,why i am getting error in questasim.
Do we neeed to add any switch while replay to support this format?
Can anyone suggest me what i can do to solve this issue
In reply to pranu:
The SystemVerilog IEEE standard only specifies how to dump/write to a VCD file. Using a VCD file as stimulus requires requires tool specific options to write it in a specific format as well as read it.
This public forum is not for tool specific support.
I am also getting “Error:Top-Level design unit “counter” does not have port y” where y is real type when VCD file has
->Parameter
->real
->integer
Eg;
$var parameter 32 % width $end
$var real 64 @ y $end