Hi,
I am getting error when re-simulating design using questasim command vsim counter -vcdstim counter.vcd
i modified bitwidth field from vector to 1 bit
Example
$var reg 8 # count [7:0] $end
modified to
$var reg 1 # count [0] $end
$var reg 1 # count [1] $end
…
$var reg 1 # count [7] $end
now its working
why i am not getting results with vector definition $var reg 8 # count [7:0] $end ?
counter.vcd file is shown below
$date
Fri Jul 29 14:00:17 2016
$end
$version
QuestaSim Version 10.0b
$end
$timescale
1ns
$end
$scope module test_counter $end
$scope module dut $end
$var parameter 32 ! tpd_reset_to_count $end
$var parameter 32 " tpd_clk_to_count $end
$var reg 8 # count [7:0] $end
var wire 1 clk $end
$var wire 1 % reset $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
dumpvars
b11 !
b10 "
bx #
0%
0
end
#5
1%
#8
b0 #
#9
0%
#10
1
#12
b1 #
#20
0$
#30
1$
#32
b10 #
#40
0$
#50
1$
#52
b11 #
#60
0$
#70
1$
#72
b100 #
#80
0$
#90
1$
#92
b101 #
#100
0$