How to replay VCD file in questasim ? getting syntax error in VCD file as $var port width must be 1(found '32')

SystemVerilog
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4

In reply to pranu:
The SystemVerilog IEEE standard only specifies how to dump/write to a VCD file. Using a VCD file as stimulus requires requires tool specific options to write it in a specific format as well as read it.

This public forum is not for tool specific support.