How to replay VCD file in questasim ? getting syntax error in VCD file as $var port width must be 1(found '32')

SystemVerilog
,
5

In reply to pranu:

Hi,

I am also getting “Error:Top-Level design unit “counter” does not have port y” where y is real type when VCD file has
->Parameter
->real
->integer
Eg;
$var parameter 32 % width $end
$var real 64 @ y $end

Can anyone help me to fix this issue

Thankyou