How to pass clock signal to a class inside a program?

SystemVerilog
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1

I have used clock signal declared inside interface and pass interface as virtual into function into a class defined inside program.

But if I add clock directly to port list of program, I don’t seem to be able to access the clock signal inside the same class at all.

Don’t know the trick and definitely haven’t spent enough time learning class rules.

Any hints?

Thanks,

2

In reply to ethan_td:

You are going to need to show us a little code. What do you mean by “I don’t seem to be able to access the clock signal”? You can’t figure out the syntax, or you are getting a compiler error, or you are not seeing the value updated?

A couple of comments about your terminology. We recommend defining all classes in a package, and then importing the package where you need to use the class. There are good exceptions to this recommendation, and your case could be one of them, but I need to see what you are trying to do.

We do not recommend the use of program blocks at any time. See Are Program Blocks Necessary? - Verification Horizons . Use a module instead.

3

In reply to dave_59:

Thanks a lot on comment out so quickly and comprehensively.

My root intention was to use interface to connect DUT, TB; And use task to generate stimuli onto interface.

So I took an example code from: Interfaces Part-X

This example works with smaller touchups. But the minute I extracted clock signal from interface definition and direct connect to program like:


program(input bit iClk, ... )
  bit bclk;
  ...
  class driver;

  function new(input bit iclk, virtual interface.tb this_if)
    this.bclk = iclk;  // tried without iclk in new()
    this.if = this_if;
  endfunction

  task run_t()
  @(negedge(bclk) ... // nothing happens here

Thanks again,

4

In reply to ethan_td:

You are only making a one-time assignment to bclk in the new constructor, but it never changes again. Why don’t you just use @(negedge iClk) in your task?

5

In reply to dave_59:

posted snippet is just one variation of my trails. My giving up point was to directly use iClk which was driven on the top by “always #5 clk = ~clk;”

Neither one seem to work, I have a $display right after @(negedge iClk); $display(“WoW…”);

program(input bit iClk, ... )
  ...
  class driver;
 
  function new(virtual interface.tb this_if)
    this.if = this_if;
  endfunction
 
  task run_t()
  @(negedge(iClk) ... // nothing happens here