How to pass clock signal to a class inside a program?

SystemVerilog
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3

In reply to dave_59:

Thanks a lot on comment out so quickly and comprehensively.

My root intention was to use interface to connect DUT, TB; And use task to generate stimuli onto interface.

So I took an example code from: Interfaces Part-X

This example works with smaller touchups. But the minute I extracted clock signal from interface definition and direct connect to program like:


program(input bit iClk, ... )
  bit bclk;
  ...
  class driver;

  function new(input bit iclk, virtual interface.tb this_if)
    this.bclk = iclk;  // tried without iclk in new()
    this.if = this_if;
  endfunction

  task run_t()
  @(negedge(bclk) ... // nothing happens here

Thanks again,