How to pass array wires from the design which will be by reference and not static?

SystemVerilog
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1

Hi there,

I have a task in which I need to check several sequences (logical not in UVM sense).

each sequence has a different set of design signals which should be checked. I created a task which checks a general sequence by the requirements needed. The issue is I need to generalize the task in order to pass different design arrays but I cannot manage to do that. the task is an automatic task (a requirement which is necessary).

My question is how do I pass a design array of wires in such way where I can monitor its changes (for example waiting for posedge or negedge)? and then perform the checks that I need.

Best Regards and thank you in advance.

2

In reply to gabi0307:

There are a couple of ways to handle this.

The straightforward approach might be to create an array of variables and use a continuous assignment from the array of wires to the array of variables, the call the task with the variable.

  wire [7:0] W[10];
  logic [7:0] V[10];
  assign V = W;
  ...
  myrask(V);

But a better methodology might be to use a module instead of task to model your checks (or place your task inside this module). You can use the bind construct to instantiate your module. This simplifies the need to create a separate array variable and continuous assignment for each check.

3

In reply to dave_59:

Hi Dave,
Thank you for the reply.

I’ve tried what you have suggested but it gives me a shallow copy (static value of design) and not a pointer to the signals themselves.

below is a pseudo code of my situation:


interface scoreboard ();
   //defines of variables
   //...
   assign design_array1 = {a1,...,an}
   assign design_array2 = {b1,...,bn}

   //later in the code

   always @ (trigger1) begin
      task_sequence1
   end
   always @ (trigger2) begin
      task_sequence2
   end

   //later in the code

   task task_sequence1 ();
      sequence_checker (/*all the arguments*/)
   endtask
   task task_sequence2 ();
      sequence_checker (/*all the arguments*/)
   endtask

   //later in the code

   task automatic sequence_checker (/*all the arguments*/);
      // implemintation of the task
   endtask

endinterface

The issue is I need sequence checker to know how to receive different design_array inputs for each sequence I have with the same verification method of sequence_checker. I hope it clarifies the issue I have.

4

In reply to gabi0307:

I don’t know what you mean by /* all the arguments */. Didn’t you want to pass design_array1 by reference?

It would help to show a minimal compete example of what you are trying to accomplish.

5

In reply to dave_59:

Hi Dave,

The sequence_checker task holds many arguments and I just didn’t want to belabor my comment. Yes my purpose is to be able to pass design_array as an argument in the following way:


sequence_checker (input logic design_array[], int SIZE, input logic expected_values[], input logic expected_values_init[], input logic expected_values_final[])

Basically those are the arguments I am passing. I’ve used “input logic” because I believed it was the correct way. If you feel this is wrong or there is a better way let me know.

Best Regards,
Gabriel.