How to pass array wires from the design which will be by reference and not static?

SystemVerilog
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2

In reply to gabi0307:

There are a couple of ways to handle this.

The straightforward approach might be to create an array of variables and use a continuous assignment from the array of wires to the array of variables, the call the task with the variable.

  wire [7:0] W[10];
  logic [7:0] V[10];
  assign V = W;
  ...
  myrask(V);

But a better methodology might be to use a module instead of task to model your checks (or place your task inside this module). You can use the bind construct to instantiate your module. This simplifies the need to create a separate array variable and continuous assignment for each check.