How to pass array wires from the design which will be by reference and not static?

SystemVerilog
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3

In reply to dave_59:

Hi Dave,
Thank you for the reply.

I’ve tried what you have suggested but it gives me a shallow copy (static value of design) and not a pointer to the signals themselves.

below is a pseudo code of my situation:


interface scoreboard ();
   //defines of variables
   //...
   assign design_array1 = {a1,...,an}
   assign design_array2 = {b1,...,bn}

   //later in the code

   always @ (trigger1) begin
      task_sequence1
   end
   always @ (trigger2) begin
      task_sequence2
   end

   //later in the code

   task task_sequence1 ();
      sequence_checker (/*all the arguments*/)
   endtask
   task task_sequence2 ();
      sequence_checker (/*all the arguments*/)
   endtask

   //later in the code

   task automatic sequence_checker (/*all the arguments*/);
      // implemintation of the task
   endtask

endinterface

The issue is I need sequence checker to know how to receive different design_array inputs for each sequence I have with the same verification method of sequence_checker. I hope it clarifies the issue I have.