Verification Academy
Error with SV Interface wrapper for Verilog DUT
SystemVerilog
Bus-interface
,
illegal-use-of-modport
,
SystemVerilog
,
modport
,
SV
AnwarSholi
April 11, 2019, 8:32am
6
In reply to
nikhil.n
:
sorry but I have the same problem, how did you solve it?
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