Error with SV Interface wrapper for Verilog DUT

In reply to sbellock:

I did it on the second line as you can see. It gives the error still.

Is it that the modport is used for synthesis purpose only and not for testbench?

//---------Wrapper------
module add_wrap(aif);

adif.dut aif;

add i_add( .a(aif.a), .b(aif.b), .sum(aif.sum), .cout(aif.cout));
endmodule

Thank you once again for your response.