Driving a wire from a task in an interface

SystemVerilog
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6

In reply to warnerrs:

I totally agree. OP’s example driver class is directly driving the wire from a class, not going through a clocking block, which I think is illegal, and is what I was pointing out. Some tools may allow that though.

I believe that driving a wire thru a task is illegal.
Quote:
1800-2012 14.3 Clocking block declaration

  • A clockvar whose clocking_direction is inout shall behave as if it were two clockvars, one input and one output, having the same name and the same clocking_signal.
  • Reading the value of such an inout clockvar shall be equivalent to reading the corresponding input clockvar.
  • Writing to such an inout clockvar shall be equivalent to writing to the corresponding output clockvar.

Here is a simple model:


module top; 
  timeunit 1ns;     timeprecision 100ps;    
    bit clk, a, b; 
    wire w;  
	 
    initial forever #10 clk=!clk; 
    task t(); 
        w = 1'b1;  // ILLEGA !!!!
    endtask
    
    initial begin
        #10; 
        t(); 
        $stop; 
    end
endmodule

On Edit code - EDA Playground
I gat “w is not a valid left-hand side of a procedural assignment.”
I also get an illegal message on other tools.
Thus, to drive a wire thru a task, you got to go thru a clocking block and modport and variable clocking_direction as inout

Ben SystemVerilog.us