In reply to ben@SystemVerilog.us:
In reply to warnerrs:
Below is a link to a simple model that demonstrates that a wire (data) in an interface can be drivern by a task in a class.
I totally agree. OP’s example driver class is directly driving the wire from a class, not going through a clocking block, which I think is illegal, and is what I was pointing out. Some tools may allow that though.