Driving a wire from a task in an interface

SystemVerilog
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In reply to ben@SystemVerilog.us:

Questions: in what version (year) of 1800 did the clocking block came about? Also, was this the result of uvm?

Clocking blocks were introduced by the 2002 Vera language donation to SystemVerilog 3.1. In Vera, you do not communicate directly with Verilog signals. It set up a PLI sampling and driving mechanism, and the clocking block was intended to replace that. This was all long before there was an AVM/OVM/UVM.