Driving a wire from a task in an interface

SystemVerilog
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In reply to dave_59:

In reply to ben@SystemVerilog.us:
It is illegal to make procedural assignments to wires. When you declare clocking block outputs, you are declaring another signal associated with the wire or variable of the same name. You use a clocking block drive statement to schedule an assignment to a clocking block output variable, which then gets assigned to the original signal.

Thanks Dave! I see the following equivalence for “data” from what you are describing
:

 clocking driver_cb @ (posedge clk);
		default input #setup_time output #hold_time;
		output rst_n, rd, wr, address; //  kind_cp; 
		input hold;
		inout data;   // <------------------- the bi-direct 
	endclocking : driver_cb
wire[31:0] data;  // <------------------- the bi-direct
Logic[31:0] data_var;  // <------------------- the cb temp

always_comb #hold_time data=data_var:
// nonblocking assignment to data is equivalent to a nonblocking assessment to data_var, and 
// then data_var gets assigned to data after a hold time, as defined in the clocking block.

Questions: in what version (year) of 1800 did the clocking block came about? Also, was this the result of uvm?
Thanks, Ben systemverilog.us