Continuous assignment vs always_comb

SystemVerilog
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1

Is there any difference between the following two codes in the hardware? assume a, b and c as single bit signals.

always_comb
a=b&c;

assign a=b&c;
2

In reply to svishnu:

  1. The always_comb cannot be used on a wire
  2. see example (1) - EDA Playground
  3. I prefer to use the always_comb for combinational logic, and the assign for assignment to wires

module m; 
  bit a, b; 
  logic l1, l2;
  wire w1, w2;
  assign a=!b;
  always_comb b=l2;
  assign l2=1'b1; 
  always_comb l1=!l2; 
  assign w1=1'b0;
  /// always_comb w2=w1; // *** ILLEGAL 
  // Net type cannot be used on the left side of this assignment.
  // The offending expression is : w2
  // Source info: w2 = w1;
endmodule

Ben@systemverilog.us

3

In reply to svishnu:

There is no difference in resulting hardware. With this simple example, it is hard to see the benefit of always_comb versus assign. The assign statement is a much lower level construct as you can only define one signal with one equation. You can be much more expressive with the always_comb.

4

I like the implications of each:

  • always_comb implies strict combinational logic
  • assign implies assignment to a wire

They both are one liner, but the connotations are different
Of course the always_comb can be more complex with the begin / end
Ben

5

In reply to ben@SystemVerilog.us:

Hello,

How about the latch infer during synthesize ?

does always_comb infer latch ?

6

In reply to kddholak:
always_comb is a declaration of intent stating that the block will consist of combinational logic only. You need to use always_latch to infer a latch.

7

In reply to svishnu:

from hardware point of view in always_comb we use the signals as reg so there maybe some storage element but in assign statement there is only single wire.

8

In reply to shanya:

In reply to svishnu:
from hardware point of view in always_comb we use the signals as reg so there maybe some storage element but in assign statement there is only single wire.

If the structure with the always_comb implies storage, the compiler will flag this as an error.
Also, if the always_ff does not imply storage, it’s an error.
The “always” can do anything.
Ben Ben@systemverilog.us