Continuous assignment vs always_comb

SystemVerilog
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2

In reply to svishnu:

  1. The always_comb cannot be used on a wire
  2. see example (1) - EDA Playground
  3. I prefer to use the always_comb for combinational logic, and the assign for assignment to wires

module m; 
  bit a, b; 
  logic l1, l2;
  wire w1, w2;
  assign a=!b;
  always_comb b=l2;
  assign l2=1'b1; 
  always_comb l1=!l2; 
  assign w1=1'b0;
  /// always_comb w2=w1; // *** ILLEGAL 
  // Net type cannot be used on the left side of this assignment.
  // The offending expression is : w2
  // Source info: w2 = w1;
endmodule

Ben@systemverilog.us