Constraint

SystemVerilog
9

For the users, who doesn’t have const() supported in constraint.

class abc;
    rand bit[23:0] AA;
    bit[23:0] AA_past = 0;
    
    constraint AA_C { $countones(AA_past ^ AA) == 16;}

    function void post_randomize();
        AA_past = AA;
    endfunction // post_randomize

endclass // abc