Constraint

SystemVerilog
22 
class jh;
  
  randc bit [24:0] g;
  
  constraint fhg{counth(g) <= 16;}
  
  function int counth(bit [24:0] j);
    foreach(j[i])
      begin
        if(i > 0)
          begin
            if(j[i-1] != j[i])
              ++counth;
          end
      end
  endfunction
  
endclass