Constraint

SystemVerilog
21

In reply to dave_59:

In reply to avpchandra:
Sorry, then maybe I should have written

   constraint AA_C { $countones(const'(AA) ^ AA) <= 16;}

But I’m not sure how you are defining a transition, Can you give a few examples and explain how you count transitions. The only example you gave was a 4-bit value, and AA is 24 bits.

Thank you for sharing. Unfortunately this syntax only works with questa!

22 
class jh;
  
  randc bit [24:0] g;
  
  constraint fhg{counth(g) <= 16;}
  
  function int counth(bit [24:0] j);
    foreach(j[i])
      begin
        if(i > 0)
          begin
            if(j[i-1] != j[i])
              ++counth;
          end
      end
  endfunction
  
endclass
23

In reply to srikanth_6313:

Instead of inserting an if-else condition Can we go with the arithmetic right shift?


class A;
    rand bit [23:0]AA;
    constraint AA_C {
      $countones(AA ^ (AA >>> 1)) <= 16;
    }
endclass
24

Hi Dave,

Could you please explain how const will behave during the first randomize call ? I understand in the subsequent randomizations the const’ will treat the value of AA as sampled from previous randomization.

25

That’s not entirely accurate. A const cast returns the value of the expression inside the cast before the solver assigns any new random values. Therefore, technically, it’s the value of the expression after the pre_randomize() function is called and before the solver assigns any values to random variables.

26

thank you