Constraint

SystemVerilog
16

In reply to srikanth_6313:

Constraint to limit the transitions in 24bit register

class A;
rand bit [23:0] AA;
constraint AA_C {  
($countones( AA ^ (AA>>1)) - 1) <= 16;
}
endclass

In reply to avpchandra:

Hi Srikanth,
Please explain in detail your solution…? Your solution is working

Thanks,