Constraint solver problem

SystemVerilog
1

I am trying to solve a constraint of instruction set where I need add instruction 20 times MUL less than 5 timed XOR less than 5 time

typedef enum int { ADD_1,SUB_1,MUL_1,NAND,DIV,AND,OR,NOR,XOR} instruction;

rand instruction inst[];


constraint size_1 {
                     
                     inst.sum with (int'(item==SUB_1) inside {0,2,8,16});
                     inst.sum with (int'(item==MUL_1) inside {[0:5]} );
                     inst.sum with (int'(item==XOR) inside {[0:5]} );
                     inst.sum with ((item==ADD_1) == 10 );
                           
               }

for ADD instruction only constraint I am seeing constraint solver Issue
Solver failed when solving following set of constraints

rand bit[30:0] inst.size(); // rand_mode = ON 
rand ex01_pkg_serial_child_sequence_11_0::instruction fv_temp_111; // rand_mode = ON 
rand bit[0:0] fv_temp_114; // rand_mode = ON 
rand bit[0:0] fv_temp_115; // rand_mode = ON 
rand bit[0:0] fv_temp_116; // rand_mode = ON 

constraint size_1    // (from this) (constraint_mode = ON) (../ex01/serial_child_sequence.sv:59)
{
   (fv_temp_116 == (inst.size() * ((fv_temp_111 == ex01_pkg_serial_child_sequence_11_0::instruction::ADD_1) == 10)));
   ((fv_temp_114 >= fv_temp_115) && (fv_temp_114 <= fv_temp_116));
   fv_temp_114;
}

if I put Add instruction inside operator it’s passing.

2

In reply to sam497:

constraint size { inst.size() inside {[80:100]};}
constraint size is 80 to 100.

3

In reply to sam497:

The sum of all instructions needs to be in the range of the size of the inst array.

4

In reply to sam497:

sorry for confusion my question is about issue coming when I constraint add to 10 over the size of 100

constraint size_1 {

inst.sum with (int'(item==SUB_1) inside {0,2,8,16});
inst.sum with (int'(item==MUL_1) inside {[0:5]} );
inst.sum with (int'(item==XOR) inside {[0:5]} );
inst.sum with ((item==ADD_1) == 10 );

}

for ADD instruction only constraint I am seeing constraint solver Issue
Solver failed when solving following set of constraints

rand bit[30:0] inst.size(); // rand_mode = ON
rand ex01_pkg_serial_child_sequence_11_0::instruction fv_temp_111; // rand_mode = ON
rand bit[0:0] fv_temp_114; // rand_mode = ON
rand bit[0:0] fv_temp_115; // rand_mode = ON
rand bit[0:0] fv_temp_116; // rand_mode = ON

constraint size_1 // (from this) (constraint_mode = ON) (…/ex01/serial_child_sequence.sv:59)
{
(fv_temp_116 == (inst.size() * ((fv_temp_111 == ex01_pkg_serial_child_sequence_11_0::instruction::ADD_1) == 10)));
((fv_temp_114 >= fv_temp_115) && (fv_temp_114 <= fv_temp_116));
fv_temp_114;
}

5

In reply to sam497:

I’m sorry, I misread your original code. It would have helped to show a complete code formatted example. The problem is with your placement of parentheses in all the sum constraints and that you did not cast item==ADD_1 to an int. Here is the corrected code.

module top;
  class istream;
  typedef enum int { ADD_1,SUB_1,MUL_1,NAND,DIV,AND,OR,NOR,XOR} instruction;
  rand instruction inst[];
  constraint size_1 {
 
    inst.sum with (int'(item==SUB_1)) inside {0,2,8,16};
    inst.sum with (int'(item==MUL_1))inside {[0:5]};
    inst.sum with (int'(item==XOR)) <=5 ;
    inst.sum with (int'(item==ADD_1)) == 10 ;
 
  }
  constraint size { inst.size() inside {[80:100]};}
endclass
  
  istream is = new;
  initial repeat(10) begin
    assert(is.randomize());
    $display("%0p",is.inst);
  end
endmodule
6

In reply to dave_59:

Thanks! Dave