I am trying to solve a constraint of instruction set where I need add instruction 20 times MUL less than 5 timed XOR less than 5 time typedef enum int { ADD_1,SUB_1,MUL_1,NAND,DIV,AND,OR,NOR,XOR} instruction; rand instruction inst[]; constraint size_1 { …

In reply to sam497 : I’m sorry, I misread your original code. It would have helped to show a complete code formatted example. The problem is with your placement of parentheses in all the sum constraints and that you did not cast item==ADD_1 to an int. Here is the corrected code. module top; class…

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Constraint solver problem

SystemVerilog

sam497 August 24, 2023, 7:06pm 2

In reply to sam497:

constraint size { inst.size() inside {[80:100]};}
constraint size is 80 to 100.