Constraint solver problem

SystemVerilog
5

In reply to sam497:

I’m sorry, I misread your original code. It would have helped to show a complete code formatted example. The problem is with your placement of parentheses in all the sum constraints and that you did not cast item==ADD_1 to an int. Here is the corrected code.

module top;
  class istream;
  typedef enum int { ADD_1,SUB_1,MUL_1,NAND,DIV,AND,OR,NOR,XOR} instruction;
  rand instruction inst[];
  constraint size_1 {
 
    inst.sum with (int'(item==SUB_1)) inside {0,2,8,16};
    inst.sum with (int'(item==MUL_1))inside {[0:5]};
    inst.sum with (int'(item==XOR)) <=5 ;
    inst.sum with (int'(item==ADD_1)) == 10 ;
 
  }
  constraint size { inst.size() inside {[80:100]};}
endclass
  
  istream is = new;
  initial repeat(10) begin
    assert(is.randomize());
    $display("%0p",is.inst);
  end
endmodule