I am trying to solve a constraint of instruction set where I need add instruction 20 times MUL less than 5 timed XOR less than 5 time typedef enum int { ADD_1,SUB_1,MUL_1,NAND,DIV,AND,OR,NOR,XOR} instruction; rand instruction inst[]; constraint size_1 { …

In reply to sam497 : I’m sorry, I misread your original code. It would have helped to show a complete code formatted example. The problem is with your placement of parentheses in all the sum constraints and that you did not cast item==ADD_1 to an int. Here is the corrected code. module top; class…

IMPORTANT NOTICE: Please be advised that the Verification Academy Forums will be offline for scheduled maintenance on Sunday, March 23rd at 4:00 US/Pacific.

Verification Academy

Constraint solver problem

SystemVerilog

dave_59 August 25, 2023, 7:25am 3

In reply to sam497:

The sum of all instructions needs to be in the range of the size of the inst array.