Complicated assertion

SystemVerilog
, ,
4

In reply to akivama:
1800 defines one of options for a sequence as:

sequence_expr ::=  
| (sequence_expr {, sequence_match_item}) [sequence_abbrev]
For example: 
property p; 
  int v; 
     (a            , v=data)                     [*2] |-> ##1 sig==data;
// (sequence_expr {, sequence_match_item}) [sequence_abbrev]
endproperty 
// for your example: 
bit[15:0] sig; 
property p; 
  bit[15:0] v;  // same type as the type for sig 
  ($rose(result_valid)) |-> 
       ##1 (1,v=sig) ##1 v==sig[*0:$] ##1 ($rose(result_valid));
// The "1" in (1, v=sig) is the sequence_expr, alwasy true to set the local variable

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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