Complicated assertion

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Hi Ben,
Thank you for your quick response.
I have some questions about your solution:
sigtype v;
(rose(result_valid)) |-> ##1 **(1,v=sig)** ##1 v==sig[*0:] ##1 ($rose(result_valid));

  1. What sigtype means?
  2. What (1,v=sig) means?