Clock generation

SystemVerilog
, ,
1

how to generate a clock of 20 MHZ from 100MHZ reference clock?

1 Like
2

See this.

Thanks & Regards,

Juhi Patel
1 Like
3

In reply to anvesh dangeti:
For a symmetrical 50/50 waveform


// how to generate a clock of 20 MHZ from 100MHZ reference clock?
// 100MHZ = period 0f 10ns, 10MHZ = period 100ns, 20MHZ = period 50ns (25 lo, 25 hi)
module clkgen; 
  timeunit 1ns;  timeprecision 100ps;  
  bit clk100, clk20;
  bit[0:4] div =5'b10000;
  initial forever #5 clk100 = !clk100;
  always @(posedge clk100)
     div <= {div[4], div[0:3]};

  always @(posedge div[4]) begin 
     clk20<= 1'b1; 
     #25 clk20 <= 1'b0;
  end
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

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1 Like
4

In reply to Juhi_Patel:

Hello,

I need help

in case my case clock is output from DUT ,i want to generate a clock in testbench which is half the time period of DUT clock

5

In reply to dddvlsique:

Hello, generally speaking your problem is kind of fout=fin/div where div in you case is: 5.

So i would say a synth module would be using a simple counter. To give you an idea:


module ckdiv#(parameter DIV=10)(input logic cki, output logic cko);
logic [31:0] cnt = 'd0;
always_ff @(posedge cki or megedge cki) begin: clkgen
 cnt <= cnt + 1'b1;
 if(cnt>=(DIV-1)) cnt <= 'd0;
 cko <= (cnt <= (DIV/2)) ? 1'b1:1'b0;
end
endmodule
1 Like
6

In reply to Rsignori92:


 //  ,i want to generate a clock in testbench which is half the time period of DUT clock
 module top;
    timeunit 1ps;  timeprecision 100fs;  
    bit clk, clk2x=1'b1;  
    initial forever #5000 clk = !clk;  // 5ns 
    initial begin
        //$timeformat [ ( units_number , precision_number , suffix_string , minimum_field_width ) ] ;
          $timeformat(-12, 4, "ps", 8);
      $display("%t", $realtime);
    end
    initial begin 
         @(posedge clk) forever #2500 clk2x=!clk2x; 
    end
  
      
    initial begin
      repeat (20) begin
        @(posedge clk); 
      end
      $finish;
    end
  endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
    Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com
  3. Papers: