Clock generation

SystemVerilog
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3

In reply to anvesh dangeti:
For a symmetrical 50/50 waveform


// how to generate a clock of 20 MHZ from 100MHZ reference clock?
// 100MHZ = period 0f 10ns, 10MHZ = period 100ns, 20MHZ = period 50ns (25 lo, 25 hi)
module clkgen; 
  timeunit 1ns;  timeprecision 100ps;  
  bit clk100, clk20;
  bit[0:4] div =5'b10000;
  initial forever #5 clk100 = !clk100;
  always @(posedge clk100)
     div <= {div[4], div[0:3]};

  always @(posedge div[4]) begin 
     clk20<= 1'b1; 
     #25 clk20 <= 1'b0;
  end
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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