In reply to dddvlsique:
Hello, generally speaking your problem is kind of fout=fin/div where div in you case is: 5.
So i would say a synth module would be using a simple counter. To give you an idea:
module ckdiv#(parameter DIV=10)(input logic cki, output logic cko);
logic [31:0] cnt = 'd0;
always_ff @(posedge cki or megedge cki) begin: clkgen
cnt <= cnt + 1'b1;
if(cnt>=(DIV-1)) cnt <= 'd0;
cko <= (cnt <= (DIV/2)) ? 1'b1:1'b0;
end
endmodule