Class inheritance for variable declaration with initial value

SystemVerilog
1

Hi folks,

Can someone help me to understand how class inheritance for variable declaration with initial value?
Specifically, for variable name, only define get_name() function, the extended class can get the updated name.


class A;
   /*const */string name = "A";

   virtual function string get_name();
      return name;
   endfunction // get_name

   virtual function void print_it();
      $display("name:%s",get_name());
   endfunction // print_it
endclass

class B extends A;
   /*const */string name = "B";

   `ifdef SUB_METHOD
   virtual function string get_name();
      return name;
   endfunction // get_name
  `endif
   
endclass // B


module tb;
   A a;
   B b;

   initial begin
      a = new();
      b = new();

      a.print_it();
      b.print_it();
   end
endmodule
2

In reply to mlsxdx:

I think oyu are confusing overwriting the initial value with adding a new class variable. Your class B adds another variable called “name” that is only visible in the extended class. That is why you needed virtual method get_name in the extended class to access it. What you could do is overwrite name in the extended constructor.

class A;
   string name = "A";
   virtual function void print_it();
     $display("name:%s",name);
   endfunction
endclass
 
class B extends A;
 function new;
   name = "B";
 endfunction
endclass
3

In reply to dave_59:

I like your idea by adding new() although it could be old, Dave.

If the variable - name is static type, then the problem comes. Both base & extended class will print out the updated value - B, which will break the pattern of class inheritance.

I came across this in UVM pkg specifically for type_name, which confuse me a lot.


class A;
   static string name = "A";
   virtual function void print_it();
     $display("name:%s",name);
   endfunction
endclass
 
class B extends A;
 function new;
   name = "B";
 endfunction
endclass // B

module tb;
   A a;
   B b;

   initial begin
      a = new();
      b = new();
      a.print_it();
      b.print_it();
   end
endmodule
4

In reply to mlsxdx:

The UVM does what your original example does with SUB_METHOD defined. Buried in the uvm_object_utils and `uvm_component_utils is

`define m_uvm_get_type_name_func(T) \
   const static string type_name = `"T`"; \
   virtual function string get_type_name (); \
     return type_name; \
   endfunction

Note that type_name is never defined in the uvm_object base class, just the virtual method get_type_name() which returns “< undefined >” if your class is not registered with the factory.

Also note the UVM improperly uses
const static to declare
type_name when it should have used
localparam. A
const declaration is a write once variable, not a true constant like a parameter or localparam.

5

In reply to dave_59:

You are correct, type_name is not defined in uvm_object base class. If the extended relation is like this in UVM, user needs to consider overriding the get_type_name() in extend class B.

uvm_object ← A ← B #(type T=int) (parameterized class)

Although B is registered with factory, m_uvm_get_type_name_func** is missing in **uvm_object_param_utils_begin.

In order to get_type_name() to print out the actual type_name for B, user needs to add `m_uvm_get_type_name_func(T) to update the initial value on type_name as well as the method - get_type_name().


`define uvm_object_utils_begin(T) \
   `m_uvm_object_registry_internal(T,T)  \
   `m_uvm_object_create_func(T) \
   `m_uvm_get_type_name_func(T) \
   `uvm_field_utils_begin(T) 

`define uvm_object_param_utils_begin(T) \
   `m_uvm_object_registry_param(T)  \
   `m_uvm_object_create_func(T) \
   `uvm_field_utils_begin(T)
6

In reply to mlsxdx:

You are getting into a completely new issue with UVM factory registration of parameterized classes with macros and the fact that they cannot use string type names. See Parameterized Classes, Static Members and the Factory Macros - Verification Horizons

7

In reply to dave_59:

Thank you for the link. Dave. It is good for me to spend some time to understand your paper.
I am done for now.