Class inheritance for variable declaration with initial value

SystemVerilog
5

In reply to dave_59:

You are correct, type_name is not defined in uvm_object base class. If the extended relation is like this in UVM, user needs to consider overriding the get_type_name() in extend class B.

uvm_object ← A ← B #(type T=int) (parameterized class)

Although B is registered with factory, m_uvm_get_type_name_func** is missing in **uvm_object_param_utils_begin.

In order to get_type_name() to print out the actual type_name for B, user needs to add `m_uvm_get_type_name_func(T) to update the initial value on type_name as well as the method - get_type_name().


`define uvm_object_utils_begin(T) \
   `m_uvm_object_registry_internal(T,T)  \
   `m_uvm_object_create_func(T) \
   `m_uvm_get_type_name_func(T) \
   `uvm_field_utils_begin(T) 

`define uvm_object_param_utils_begin(T) \
   `m_uvm_object_registry_param(T)  \
   `m_uvm_object_create_func(T) \
   `uvm_field_utils_begin(T)