Class inheritance for variable declaration with initial value

SystemVerilog
4

In reply to mlsxdx:

The UVM does what your original example does with SUB_METHOD defined. Buried in the uvm_object_utils and `uvm_component_utils is

`define m_uvm_get_type_name_func(T) \
   const static string type_name = `"T`"; \
   virtual function string get_type_name (); \
     return type_name; \
   endfunction

Note that type_name is never defined in the uvm_object base class, just the virtual method get_type_name() which returns “< undefined >” if your class is not registered with the factory.

Also note the UVM improperly uses
const static to declare
type_name when it should have used
localparam. A
const declaration is a write once variable, not a true constant like a parameter or localparam.