Class inheritance for variable declaration with initial value

SystemVerilog
3

In reply to dave_59:

I like your idea by adding new() although it could be old, Dave.

If the variable - name is static type, then the problem comes. Both base & extended class will print out the updated value - B, which will break the pattern of class inheritance.

I came across this in UVM pkg specifically for type_name, which confuse me a lot.


class A;
   static string name = "A";
   virtual function void print_it();
     $display("name:%s",name);
   endfunction
endclass
 
class B extends A;
 function new;
   name = "B";
 endfunction
endclass // B

module tb;
   A a;
   B b;

   initial begin
      a = new();
      b = new();
      a.print_it();
      b.print_it();
   end
endmodule