Checking a clock using SVA

SystemVerilog
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In reply to chitlesh:

In reply to ben@SystemVerilog.us:
Hi Ben,
Don’t you think it is better to use realtime instead of time datatype?
I feel that realtime allows one to reuse of assertions for gate-level simulations.

Yes, realtime is better.

	property p_clk_hi; 
	  realtime v; 
	  @(posedge clk) (1, v=$realtime) |-> @(negedge clk) ($realtime-v)==300ns;
	endproperty 
	ap_clk_hi: assert property(p_clk_hi);  
		
	property p_clk_lo; 
	  realtime v; 
	  @(negedge clk) (1, v=$time) |-> @(posedge clk) ($realtime-v)==700ns;
	endproperty 
    ap_clk_lo: assert property(p_clk_lo);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448