Check clock is stable for 1us before signal is asserted

SystemVerilog
, ,
2

In reply to Ankit Bhange:
Your requirements are a bit ambiguous. Below is one possibility where upon a “go” signal, there must be T number of ns before sigal “a” goes to 1’b1.
The model needs tuning to address the condition when “a” occurs.
It is modeled after my other model in
https://verificationacademy.com/forums/systemverilog/data-stable-throughout-clock-cycle/no-glitch


import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
    bit clk, a, go;  
    event e, e0, e1; 
	initial forever #5 clk=!clk; 
    /* I am trying to write an assertion that should make sure that the clock is stable 
    (frequency is constant) for 1us before a signal is asserted.
    I have another faster reference clock that can be used to write the assertion. 
    Is there any way to write the assertion when the expected clock period is not known? */

    let T=100ns; // or 1us 
    task automatic t_count();
        int count;
        fork
            fork1: begin 
                -> e0; 
                forever begin 
                    @(posedge clk) count += 1'b1;  
                end  
                //disable fork2;               
            end
            fork2: begin                
                #T; 
                disable fork1; 
                -> e1;            
            end
            fork3: begin 
                 @(posedge a); // "a" signal is asserted.
                 disable fork1; 
                 disable fork2;
            end
        join_any
        $display("%t count= %d ", $realtime, count);  
        a_t_count: assert (count >9 &&  count < 11)  else -> e; 
    endtask
	
    always @(go)  t_count(); 

	initial begin 
        #35 go <= 1'b1; 
        #20 a <= 1'b1;
    end 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers: