In reply to ben@SystemVerilog.us:
Thank you, Ben.
Please comment on the solution below:
logic CLK; //expected frequency is 100Mhz
logic stable_CLK;
realtime period;
realtime current_time;
task freq_monitor();
@(posedge CLK) current_time = $realtime;
@(posedge CLK) period = $realtime - current_time;
endtask
//reset period after waiting for 10 times CLK period after the last negedge of CLK
task reset_period;
fork begin
fork
begin
@(negedge CLK);
@(posedge CLK);
end
begin
#100ns; //10*period for 100MHz
period = 0;
end
join_any
disable fork;
end
join
endtask
initial forever freq_monitor();
initial forever reset_period();
//10000 because the ref_clk is 2GHz
assign stable_CLK = period <= 10000*1.01 && period >= 10000*0.99 ? 1 : 0;
property sig1_high_for_1us_before_sig2 (logic sig1, sig2);
disable iff (!rstb)
$rose(|sig1) && !sig2 |-> !sig2[*2000];
endproperty //sig1_stable_for_1us_before_sig2
//ref_clk is 2GHz
CLK_stable_for_1us_before_A: assert property (@(posedge ref_clk) sig1_high_for_1us_before_sig2 (stable_CLK , A));
Thanks,
Ankit