Data stable throughout a clock cycle // NO GLITCH

This is a response to a question. Generally, this is not done, but the solution is interesting and a bit challenging.
SystemVerilog.us/fv/glitchclk.sv


import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
	bit clk, a, w;  
    event e, e0, e1; 
	initial forever #10 clk=!clk; 
    
    task automatic glitch();
        bit err=0;
        fork
            fork1: begin 
                -> e0; 
                @(posedge clk);   
                disable fork2;               
            end
            fork2: begin    
                @(a); 
                disable fork1; 
                err=1;  
                -> e1;            
            end
        join_any
        // $display("%t @join %t, err=%b", $realtime, $realtime, err); 
        if(err) begin 
              a_glitch: assert (!err)  else $display("%t ERROR: Glitch in a", $realtime); 
                -> e; 
        end        
    endtask
	
    always @(a)  glitch(); 

	always  @(posedge clk)  begin 
	   automatic bit va, vd; 
	   if (!randomize(va, vd)  with 
	   		{ va dist {1'b1:=2, 1'b0:=1};
	   		  vd dist {1'b1:=1, 1'b0:=2};
	   		}) `uvm_error("MYERR", "This is a randomize error")	 
        if(vd) begin 
            #2 a <= !va;
            #1 a <= va; 
        end 
        else a <= va;  
	end 	
endmodule  

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books: Component Design by Example https://rb.gy/9tcbhl
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers:

In reply to ben@SystemVerilog.us:
A linkedIn user provided an alternate code to check that the clock half-cycles are within specs with no glitches. It is another approach.
I added 2 assertions to the code; you obviously appreciate the reduction in code when using SVA.

let halfp = clk_period_half * 1ns; 
property p_clk0; 
  realtime t;
  @(negedge clk) !pause |-> (1, t=$realtime) ##1 @(posedge clk) $realtime-t == halfp;
endproperty 
ap_clk0: assert property(p_clk0);  

property p_clk1; 
    realtime t;
    @(posedge clk) !pause |-> (1, t=$realtime) ##1 @(negedge clk) $realtime-t == halfp;
endproperty 
ap_clk1: assert property(p_clk1);   

http://SystemVerilog.us/fv/clk_chk.sv

** Error: [POS_EDGE_CHECK] transition expected 5 , observed 1

Time: 96 ns Scope: test.i_checker File: C:/ben_play/clk_chk.sv Line: 52

** Error: Assertion error.

Time: 96 ns Started: 95 ns Scope: test.i_checker.ap_clk0 File: C:/ben_play/clk_chk.sv Line: 11 Expr: $realtime()-t==511ns

Local vars : t = 95

** Error: [NEG_EDGE_CHECK] transition expected 5 , observed 1

Time: 147 ns Scope: test.i_checker File: C:/ben_play/clk_chk.sv Line: 70

** Error: Assertion error.

Time: 147 ns Started: 146 ns Scope: test.i_checker.ap_clk1 File: C:/ben_play/clk_chk.sv Line: 17 Expr: $realtime()-t==511ns

Local vars : t = 146


Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books: Component Design by Example https://rb.gy/9tcbhl
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers: