This is a response to a question. Generally, this is not done, but the solution is interesting and a bit challenging.
SystemVerilog.us/fv/glitchclk.sv
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, a, w;
event e, e0, e1;
initial forever #10 clk=!clk;
task automatic glitch();
bit err=0;
fork
fork1: begin
-> e0;
@(posedge clk);
disable fork2;
end
fork2: begin
@(a);
disable fork1;
err=1;
-> e1;
end
join_any
// $display("%t @join %t, err=%b", $realtime, $realtime, err);
if(err) begin
a_glitch: assert (!err) else $display("%t ERROR: Glitch in a", $realtime);
-> e;
end
endtask
always @(a) glitch();
always @(posedge clk) begin
automatic bit va, vd;
if (!randomize(va, vd) with
{ va dist {1'b1:=2, 1'b0:=1};
vd dist {1'b1:=1, 1'b0:=2};
}) `uvm_error("MYERR", "This is a randomize error")
if(vd) begin
#2 a <= !va;
#1 a <= va;
end
else a <= va;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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- SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
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Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb - Papers:
- Understanding the SVA Engine,
Verification Horizons - SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue - SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment